(a) Field of the Invention
The present invention relates to a semiconductor device having a miniaturized transistor, and particularly to a measure against an optical proximity effect.
(b) Description of the Related Art
Main factors causing variations in propagation delay time in a design of a semiconductor integrated circuit (LSI) include variations in operating power supply voltage, temperature, process, etc. The LSI should be designed so that its operation is ensured even when all the factors are worst. Among determinants of a transistor, the gate length is a particularly important determinant which defines the operation of the transistor. The variations in the gate length thus affect variations in process greatly. As the transistor is reduced in size, the gate length has been becoming much shorter and the variations in the gate length have been widening. As a result, the variations in propagation delay time have also widened and the design margin has increased, and thereby it has become difficult to provide the LSI having high performance.
In general, in a semiconductor fabricating process, a photolithographic step including resist application, light exposure and development, an etching step for patterning the elements with a resist mask, and a resist removing step are repeated to form an integrated circuit on a semiconductor substrate. In forming a gate of the transistor, the photolithographic step, the etching step and the resist removing step are also performed. In the exposure of the photolithographic step, if the pattern dimension is not more than the exposure wavelength, the optical proximity effect generated by the influence of diffracted light causes a large error between the pattern dimension in the layout design and the actual pattern dimension on the semiconductor substrate.
Techniques for solving the above problems include a super resolution technique using a phase shift mask and an OPC (Optical Proximity Correction) technique for correcting the influence of the optical proximity effect by modifying a circuit pattern drawn on the mask (see e.g., Japanese Unexamined Patent Publication No. H08-272075). However, the optical proximity effect inevitably occurs, and it is difficult to prevent the optical proximity effect only by manufacturing and process techniques such as the super resolution technique and the OPC technique. Therefore, a structure of the semiconductor device which can utilize to the optical proximity effect is desired at the design stage.
As previously mentioned, as the transistor is reduced in size, the gate length becomes shorter and the optical proximity effect caused by diffracted light more affects the gate in exposing the gate to light. The optical proximity effect in the formation of the gate occurs depending on the layout pattern of the gate of the transistor, and causes not only variations in the gate length among the transistors but variations in the gate length along the gate width direction. Particularly, assume that a continuous gate polysilicon film includes a gate electrode part which is a transistor element existing on an active region; a gate interconnect part extending from the gate electrode part onto an element isolation region; and a pad for forming a contact which connects the gate interconnect and an interconnect provided in an upper level. In this case, a reflex angle at the boundary between the pad and the gate interconnect part is rounded due to the optical proximity effect, which causes errors in the dimension of the gate electrode part provided on the active region, namely in the gate length of the transistor.
FIGS. 7A and 7B are a plan view illustrating the design geometry of a known semiconductor device (e.g., standard cell) and a plan view illustrating the geometry of the known semiconductor device after fabricated, respectively.
As shown in FIG. 7A, in the known semiconductor device, a gate polysilicon film is provided across a P-type diffusion region and an N-type diffusion region which are surrounded with an element isolation region made of STI or the like. Of the gate polysilicon film provided across the P-type and N-type diffusion regions and the element isolation region, parts located on the P-type and N-type diffusion regions serve as gate electrode parts (gates) G101, a part located on the element isolation region serves as a gate interconnect part G102. A rectangular enlarged part having a large area near the center of the gate interconnect part G102 serves as a contact pad G103, and the contact pad G103 includes a contact C103 connecting the gate interconnect part G102 and an interconnect provided in an upper level. The P-type diffusion region is provided with a P-type transistor with a gate G101 having a gate width W1 and a gate length L, and the N-type diffusion region is provided with an N-type transistor with a gate G101 having a gate width W2 and a gate length L. In addition, the P-type diffusion region is provided with source/drain contacts C101 and C102 and the N-type diffusion regions is provided with source/drain contacts C104 and C105.
FIG. 7B illustrates the geometry of a semiconductor device which has been actually formed on the semiconductor substrate by subjecting the semiconductor device having the design geometry illustrated in FIG. 7A to a semiconductor device manufacturing process including a photolithographic step, an etching step and a resist removing step. As shown in FIG. 7A, the boundary between the gate interconnect part G102 and the contact pad G103 has a reflex angle rounded under the influence of the optical proximity effect when exposed to light. Accordingly, as shown in FIG. 7B, the end of the diffusion region located on the side near the contact pad G103 has a gate length of L′+ΔL of which ΔL is an error with respect to the desired gate length L′ on the design geometry. It is possible to suppress the error of the gate length caused by the optical proximity effect by keeping a sufficient distance between the contact pad G103 and the diffusion region. However, this increases the area of the semiconductor device, decreases integration density, and hence is not practical.